Method of lateral oxidation of nfet and pfet high-k gate stacks

ABSTRACT

A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.

DOMESTIC PRIORITY

This application is a division of U.S. patent application Ser. No.15/892,884, filed Feb. 9, 2018, which is a division of U.S. patentapplication Ser. No. 15/247,999, filed Aug. 26, 2016, now U.S. Pat. No.9,941,128, which is a continuation of U.S. patent application Ser. No.14/604,916, filed Jan. 26, 2015, now U.S. Pat. No. 9,466,492, whichclaims priority to U.S. Provisional Application No. 61/987,620, filedMay 2, 2014, each application is incorporated herein by reference in itsentirety.

BACKGROUND

The present invention relates generally to semiconductor structures andmethods for fabricating those structures. Particularly, the inventionrelates to a semiconductor structure and a method for laterallyoxidizing nFET high-k gate stacks.

As integrated circuits become smaller, maintaining semiconductor deviceperformance and controlling threshold voltage becomes more difficult.Field Effect Transistors (FET), which lie at the core of an integratedcircuit, typically are characterized by being of a hole conduction type,called pFET, or being of an electron conduction type, called nFET. It isknown in the art that decreasing the size of a FET device leads to adecrease in controlling their performance. This is due in part to thethickness of the gate dielectric component becoming thinner as the sizeof the FET device decreases. Once the gate dielectric becomes too thinleakage begins to reach unacceptable levels and large currents may beable to flow through the dielectric material via direct tunneling. As aresult, improving semiconductor device performance without decreasingthe thickness of the gate dielectric has become increasingly important.

As is known to those skilled in the art of semiconductor design andfabrication, one such method for improving performance of a FET whilemaintaining adequate gate dielectric thickness is by replacing thetraditional gate dielectric material with another material having anacceptable equivalent oxide thickness (EOT). An acceptable EOT isachieved by using a material that has a greater dielectric capacitancethan the traditional gate dielectric material, thereby permitting thesubstitute material to have a greater thickness while maintaining areaction speed comparable to that of the traditional gate dielectricmaterial. Suitable materials are characterized as having a highdielectric constant, “k”. Accordingly such materials are known in theart as “high-k” materials. A high-k value is one that is greater thanthe dielectric constant of the traditional gate dielectric materialsilicon dioxide, which is approximately 3.9. While high-k materials mustprovide an increased dielectric capacitance, utilizing such materials isknown in the art to often result in a threshold voltage (V_(T)) that isdifferent from what is desirable from a circuit perspective. As aresult, a method for controlling V_(T) of high-k gate dielectric FETdevices has become increasingly sought after.

Controlling V_(T) in high-k dielectric FET devices is particularlysignificant for complementary metal oxide semiconductor (CMOS) devicesbecause CMOS devices operate at lower voltages, and as the operatingvoltage of a semiconductor device decreases, V_(T) also must decrease,and consequently, variations in V_(T) become less tolerable. V_(T) isaffected by known factors, but as the size of FET devices has decreased,the traditional methods of setting V_(T) (i.e., adjusting body andchannel doping) have become less effective. One method for controllingV_(T) with high-k gate dielectric FET devices utilizes an additionalmaterial layer known in the art as a “capping layer”. However cappinglayers can have undesirable effects, such as increasing EOT or degradingcarrier mobility. Furthermore, different capping layers are oftendesired for n-type FET (nFET) and p-type FET devices (pFET) devices,requiring complex and costly integration schemes.

Another known method for controlling V_(T) that remains promising isoxidation of the gate dielectric. Oxidation of the high-k dielectriclayer directly affects V_(T) and has proven to be very effective forintentionally tuning V_(T) of FET devices. However, while oxidation ofhigh-k gate stacks is known to benefit the V_(T) of p-type FET devices(pFET), it also is commonly thought to degrade the V_(T) of nFETdevices. Unintentionally filling oxygen vacancies in nFET gate stacksduring device processing can make the V_(T) of the resulting nFETdevices dependent on device-width. Therefore, not only must fabricationof CMOS devices be tailored to prevent oxidation processes that benefitpFET devices from also oxidizing nFET gate stacks, but fabricationprocesses must also be selected to prevent nFET gate stacks from beingunintentionally exposed to processes and environments that may result indevice-width dependence.

The prior art includes methods for fabricating semiconductor circuitscontaining both nFETs and pFETs (e.g., CMOS circuits) that involveexposing high-k dielectric layers of gate stacks to oxygen if those gatestacks are intended to be fabricated into pFETs, while simultaneouslykeeping high-k dielectric layers of other gate stacks unexposed tooxygen if the other gate stacks are intended to be fabricated intonFETs. These methods frequently require the implementation of additionalprocessing steps and materials for the sole purpose of regulating whichgate stacks are, and are not, exposed to oxidation processes as well asunfavorable environments, which in turn increases the complexity andexpense of fabricating semiconductor devices containing both nFETs andpFETs.

SUMMARY

According to an aspect of the present invention, a method is providedfor fabricating a semiconductor circuit. The method includes obtaining asemiconductor structure having a gate stack of material layers includinga high-k dielectric layer; oxidizing in a lateral manner the high-kdielectric layer, such that the oxygen content of the high-k dielectriclayer is increased first at the sidewalls of the high-k dielectriclayer; and completing fabrication of a n-type field effect transistorfrom the gate stack after laterally oxidizing the high-k dielectriclayer of the gate stack.

The present invention also provides another method for creating asemiconductor circuit. The method includes obtaining a semiconductorstructure having a first gate stack and a second gate stack, eachcontaining material layers that include a high-k dielectric layer;oxidizing in a lateral manner (i) the high-k dielectric layer of thefirst gate stack, such that the oxygen content of the high-k dielectriclayer of the first gate stack increases first at the sidewalls of thehigh-k dielectric layer of the first gate stack, and (ii) the high-kdielectric layer of the second gate stack, such that the oxygen contentof the high-k dielectric layer of the second gate stack increases firstat the sidewalls of the high-k dielectric layer of the second gatestack; and fabricating (i) a n-type field effect transistor from thefirst gate stack after laterally oxidizing at least the high-kdielectric layer of the first gate stack, and (ii) a p-type field effecttransistor from the second gate stack after laterally oxidizing at leastthe high-k dielectric layer of the second gate stack.

The present invention further provides a semiconductor structure. Thestructure includes an n-type field effect transistor having a high-kdielectric layer that has higher concentration of oxygen at thesidewalls of the high-k dielectric layer than at the center of thehigh-k dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view of a preferred initial semiconductorstructure according to an embodiment of the obtaining step of thepresent invention, such that the initial semiconductor structureincludes a gate stack of material layers having a layer of high-kdielectric material and the gate stack is exposed to the fabricatingenvironment.

FIG. 2 is a cross sectional view of the initial semiconductor structurein FIG. 1 before material (sidewall spacers) has been removed from thesidewalls of the gate stack in order to provide a preferred initialsemiconductor structure.

FIG. 3 is a cross sectional view of semiconductor structure in FIG. 1some time after the preferred lateral oxidation anneal process has begundiffusing oxygen at the sidewalls of the high-k dielectric layer.

FIG. 4 is a cross sectional view of the semiconductor structure in FIG.2 after the preferred lateral oxidation anneal process has diffusedoxygen into the sidewalls of the high-k dielectric layer towards thecenter of the high-k dielectric layer and stopping after partiallyoxidizing the high-k dielectric layer.

FIG. 5 is a cross sectional view of the semiconductor structure in FIG.2 after the preferred lateral oxidation anneal process has diffusedoxygen into the sidewalls of the high-k dielectric layer, achievingcomplete lateral oxidation of the high-k dielectric layer.

FIG. 6 is a cross sectional view of the semiconductor structure of FIG.2 some time after the preferred lateral oxidation process has begundiffusing oxygen into the sidewalls of the high-k dielectric layer andthe work-function conductor layer.

FIG. 7 is a cross sectional view of the semiconductor structure of FIG.5 after sidewall spacers have been fabricated in contact with thesidewalls of the gate stack.

FIG. 8 is a cross section view according to a preferred embodiment ofthe initial semiconductor of the obtaining step of the present inventionwhere the semiconductor structure includes two gate stacks of materiallayers, each having a layer of high-k dielectric material, one being ann-FET gate stack and the other being a p-FET gate stack.

FIG. 9 is a cross sectional view of the semiconductor structure in FIG.8 slightly after lateral oxidation has begun diffusing oxygen at thesidewalls of the high-k dielectric layers of both gate stacks.

FIG. 10 is a cross sectional view of the semiconductor structure in FIG.9 after achieving complete lateral oxidation of the high-k dielectriclayers in both gate stacks.

FIG. 11 is a cross sectional view of the semiconductor structure of FIG.11 after spacers have been added to the sidewalls of both gate stacks.

FIG. 12 is a cross sectional view of a semiconductor structure accordingto an embodiment of the present invention where the semiconductorstructure includes two gate stacks of material layers, each having ahigh-k dielectric material layer, one being a n-FET gate stack and onebeing a p-FET gate stack, after the high-k dielectric layer of the n-FETgate stack has been completely laterally oxidized and the high-kdielectric layer of the p-FET gate stack has been partially laterallyoxidized.

FIG. 13 is a cross sectional view of a semiconductor structure accordingto an embodiment of the present invention where the semiconductorstructure includes two gate stacks of material layers, each having ahigh-k dielectric material layer, one being a n-FET gate stack and onebeing a p-FET gate stack, after the high-k dielectric layer of the n-FETgate stack has been completely laterally oxidized and the high-kdielectric layer of the p-FET gate stack has been partially laterallyoxidized.

FIG. 14 is a cross sectional view of a semiconductor structure accordingto an embodiment of the present invention where the semiconductorstructure includes two gate stacks of material layers, each having ahigh-k dielectric material layer, one being a n-FET gate stack and onebeing a p-FET gate stack, after the high-k dielectric layer of the n-FETgate stack has been partially laterally oxidized and the high-kdielectric layer of the p-FET gate stack has been completely laterallyoxidized.

FIG. 15 is a cross sectional view of a semiconductor structure accordingto an embodiment of the present invention where the semiconductorstructure includes two gate stacks of material layers, each having ahigh-k dielectric material layer, one being a n-FET gate stack and onebeing a p-FET gate stack, after the high-k dielectric layer of the n-FETgate stack has been partially laterally oxidized and the high-kdielectric layer of the p-FET gate stack has been partially laterallyoxidized.

DETAILED DESCRIPTION

It will be readily understood that the components of the presentinvention, as generally described and illustrated in the figures herein,may be arranged and designed in a wide variety of differentconfigurations in addition to the described presently preferredembodiments. Thus, the following detailed description of the embodimentsof the present invention, as represented in the figures, is not intendedto limit the scope of the invention, as claimed, but is merelyrepresentative of selected presently preferred embodiments of theinvention. The following description is intended only by way of example,and simply illustrates certain selected presently preferred embodimentsof the invention as claimed herein.

Fabrication of semiconductor devices containing both nFETs and pFETs,such as CMOS devices, typically requires some processes utilized solelyfor creating pFETs and others utilized solely for creating nFETs. Thisis due to the differences in electrical properties that distinguishnFETs from pFETs, such as V_(T). nFETs call for a positive V_(T), whilepFETs require a negative V_(T). This dichotomy typically dictates thatthe respective gate stacks include different materials, or commonmaterials that have been doped differently. The need to maintain thedifferent characteristic properties of each FET device requires each tobe accordingly isolated from processes that are detrimental tomaintaining such properties but that benefit the properties of the othertype of FET device. Isolating gate stacks from detrimental processesrequires additional process steps, such as the addition of protectivematerial layers that are immune to the detrimental processes.

Specifically, the process of exposing gate stacks containing metal gatesand high-k dielectrics to oxygen has been one such process that has beenaccepted within the industry as requiring isolation of gate stacks thatare intended for nFET fabrication. The reasoning behind this conclusionis that exposing a material within a gate stack to oxygen causes chargeddefects to fill, which results in a shift in work-function of thatmaterial and consequently a shift in the V_(T) of the FET device. Ascharged defects are filled, the V_(T) of the eventual gate becomes morepositive. This benefits pFETs by reducing the V_(T) to a smallernegative voltage, but adversely affects nFETs by enlarging the V_(T) toa greater positive voltage. Furthermore, unintentionally filling chargeddefects within an nFET during fabrication processes is known in the artto often result in V_(T) becoming device-width dependent.

It would be preferable if the V_(T) of both FET device types could betuned in a way that reduces the complexity and the expense of typicaldual-semiconductor-device fabrication, and in a way that avoidsadversely affecting the properties of either FET device type.Embodiments of the present invention teach semiconductor-devicestructures and fabrication methods that utilize the unconventionalprocess of subjecting nFET gate stacks to an anneal in an oxygenenvironment such that the V_(T) of the nFET gate stack is tuned whilesimplifying the overall semiconductor-device fabrication, reducing thecost of fabrication, and decreasing the risk of adversely affecting nFETV_(T) via unintentionally filling oxygen vacancies in the nFET gatestack during fabrication processes.

The present invention allows for the V_(T) of the FETs involved in aCMOS device to be tuned to the desired values through selectingmaterials for the nFET and pFET devices, subjecting the materials in thegate stacks of the nFET and pFET devices to oxidation anneal processes,and doing so at temperatures, pressures, and times that result in thedesired V_(T) levels for each FET device.

Reference is first made to FIGS. 1-7 which illustrate one of theembodiments of the present invention. It is emphasized that in thedrawings of the present application, the semiconductor structuresinclude at least one nFET device. The present invention furtherdiscloses semiconductor structures that also include a pFET, or acombination of a plurality of at least one nFET and at least one pFET.

Referring to FIG. 1, an embodiment of the present invention isillustrated. The embodiment includes a semiconductor structure 100having at least one FET device 101 that includes a gate stack 110. It isunderstood that field effect transistor device structures often alsocontain standard components, such as Raises Source/Drain 104, aSemiconductor Layer 103, an Insulator Layer 102, and Sidewall Spacers108. The FET device 101 of the semiconductor structure 100 includes agate stack 110 that is disposed on a semiconductor layer 103 and thatcontains a high-k dielectric layer 105. The gate stack also includes agate-insulating layer 109, a work-function conductor layer 106 and agate conducting layer 107.

The semiconductor layer 103 can be any semiconductor material, eitherdoped or undoped, including but not limited to silicon, silicongermanium, germanium, silicon carbide, a III-V compound semiconductor, aII-VI compound semiconductor, a carbon-based semiconductor such as acarbon nanotube or graphene, an organic semiconductor, or any multilayeror other combination of these. The present invention has applicabilityto both semiconductor-on-insulator (e.g. silicon-on-insulator, SOI) andbulk semiconductor technology.

The high-k dielectric layer 105 is preferably a selection of dielectricmaterial with a higher dielectric constant than SiO₂ including at leastone metallic element, such as hafnium oxide (HfO₂), zirconium oxide(ZrO₂), aluminum oxide (Al₂O₃), hafnium silicate (HfSiO), nitridedhafnium silicate (HfSiON), hafnium oxynitride (HfO_(x)N_(y)), lanthanumoxide (La₂O₃), lanthanum aluminate (LaAlO₃), zirconium silicate(ZrSiO_(x)), and any other dielectric material having a dielectricconstant higher than that of SiO₂. As such, the high-k dielectric layer105 can be a selected single material or can be a selection of differentdielectric materials, which can be intermixed preferably resulting in avertical composition gradient having a compositional depth profile ofmetal ion density.

The work-function conductor layer 106 is preferably in contact with thehigh-k dielectric layer 105. The work-function conductor layer can bemade of a conductive refractory metal nitride, such as titanium nitride(TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN),tantalum aluminum nitride (TaAlN), any combinations thereof, as well asother materials.

In the example semiconductor structure 100 shown in FIG. 1, agate-conducting layer 107 is included in contact with the work-functionconductor layer 106 in gate stack 110. The gate-conducting layer 107 ofgate stack 110 can be made of such materials as amorphous silicon, anamorphous silicon containing alloy, polycrystalline silicon, apolycrystalline silicon containing alloy, a silicide, a silicide onsilicon combination, tungsten, titanium nitride, tantalum nitride, anyother conducting material, or any combination or multilayer stack ofconducting materials. Exemplary silicon containing alloys are silicongermanium alloy, silicon carbon alloy, and silicon germanium carbonalloy. Additionally, the gate-conducting layer may be doped withdopants, such as n-type or p-type dopants depending on the intendedfunctionality of the gate stack.

Referring to FIG. 1, further parts of semiconductor 100 are the raisedsource/drain regions 104 of the FET device 101, as well as the sidewallspacers 108. The sidewall spacers 108 are in contact with opposite sidesof the gate stack 110 and in contact with the semiconductor layer 103.The sidewall spacers 108 are preferably in direct contact with allmaterial layers of the gate stack 110 of the FET device 101. The raisedsource/drain regions 104 are disposed on the semiconductor layer 103adjacent to each sidewall spacer 108 of gate stack 110.

In a preferred embodiment of the present invention, insulator layer 102is of SiO₂, semiconductor layer 103 is of Si, raised source/drain 104 isalso of Si, gate-insulating layer 109 is of SiO₂, high-k dielectriclayer 105 includes HfO₂, work-function conductor layer 106 includes TiN,gate-conductor layer 107 is of silicide on Si, and sidewall spacers 108are of Si₃N₄.

Manufacturing of nFET, pFET and CMOS structures is very well establishedin the art. It is understood that there are a large number of stepsinvolved in such processing, and each step might have practicallyendless variations known to those skilled in the art. Many possiblemethods of fabrication that lead to a structure as in FIG. 1 are knownin the art. For example, see U.S. Pat. No. 7,488,656 for a descriptionof one possible method of fabricating a high-k dielectric metal gateCMOS semiconductor structure. Furthermore, a vast range of knownprocessing techniques are available for fabricating the initialsemiconductor structures of the present invention.

As is known in the art, performing a dopant activation anneal on a gatestack at a high temperature affects the composition of the high-kdielectric materials in the gate stack such that a loss of oxygen in thedielectric materials occurs due to decomposition. As a result,semiconductor structures intended for the present invention must nothave dopant activation anneal processes, such as those occurring above800° C., carried out after the oxidation anneal process of the presentinvention is applied. Accordingly, any dopant activation anneal processthat is required for processing of the semiconductor structures intendedfor the present invention must be carried out prior to the process ofapplying the oxidation anneal of the present invention.

Referring to FIG. 2, an initial semiconductor structure of the presentinvention is illustrated where the n-FET device 101 of the semiconductorstructure 100 has had the sidewall spacers 108 removed from thesidewalls of the n-FET gate stack 110. In order to prepare the n-FETdevice for application of an oxidation anneal, a process for selectivelyremoving material from a semiconductor structure, many of which are wellknown in the art, may be used to remove the sidewall spacers 108 fromthe semiconductor structure 100, such as those utilizing masks andetches involving diluted HF.

The exemplary semiconductor structure is oxidized by being subjected toan anneal in an oxidizing environment preferably comprising oxygenatoms, oxygen ions, or oxygen-containing molecules such as molecularoxygen (O₂), water vapor (H₂O), nitric oxide (NO), nitrous oxide (N₂O),or any other suitable oxidizing species, as shown in FIG. 3, in order toachieve the desired extent of lateral oxidation of at least the high-kdielectric layer 105, as shown in FIGS. 4, 5 and 6. The temperature ofthe preferred anneal may be from approximately 300° C. to about 600° C.,and preferably from about 400° C. to about 500° C. The oxygen partialpressure may be from approximately 100 mTorr to about 20 atm, andtypically from 0.1 atm to about 1 atm. Other partial pressures that arelesser than or greater than the aforementioned partial pressure rangecan also be employed. The duration of the oxidation anneal may be fromabout 10 minute to about 6 hours. Other durations that are lesser thanor greater than the aforementioned duration range can also be employed.In general, the preferred duration of the anneal decreases with anincrease in either the anneal temperature, or the partial pressure ofthe oxygen environment involved, or both. The temperature, pressure andduration of the anneal process may be correspondingly chosen to achievethe desired extent of oxidation of the high-k dielectric layer 105.Furthermore, the oxidation anneal process may be carried out throughmultiple process at various pressures, temperatures, and durations, asthis may be advantageous to achieve a more complete oxidation of thehigh-k dielectric layer 105.

FIG. 3 illustrates a step of the present invention in which the exposedgate stack 110 of the n-FET device 101 is subjected to a process toachieve lateral oxidation, such that oxygen diffuses into at least thehigh-k dielectric layer 105. In FIG. 3, the high-k dielectric layer 105of the FET device 101 is shown with arrows indicating that the lateraloxidation process is characterized by affecting the oxygen content ofthe high-k dielectric layer 105 first at the sidewalls of the gate stack110 and continues to diffuse oxygen in towards the center of the gatestack 110 as the duration of the process continues.

During the preferred oxidation anneal process, atomic oxygen, or oxygenmolecules, or both, diffuse into at least the high-k dielectric layer105. The effects of the diffusion on the gate stack 110 are illustratedin FIG. 4, FIG. 5, and FIG. 6, in which the atomic oxygen and/or oxygenmolecules are incorporated into the high-k dielectric layer. The oxygencontent of the high-k dielectric layer first increases at the sidewallsof the gate stack 110 which are immediately exposed to the oxidationanneal environment and thereafter the oxygen content continues toincrease towards the center of the gate stack 110 as the duration of theoxidation anneal continues.

Referring to FIG. 4, the high-k dielectric layer 105 is shown as havingan oxygen content that is higher near the edge than near the center ofthe high-k dielectric layer. The high-k dielectric layer 105 haspreferably been subjected to a lateral oxidation anneal process at apressure and temperature, as well as for a duration, to cause oxygen todiffuse into the high-k dielectric layer 105 and result in partiallyoxidizing the high-k dielectric layer 105 such that the oxygen does notdiffuse to the center of the nFET gate stack 110.

Referring to FIG. 5, the high-k dielectric layer 105 is shown as havingoxygen diffused throughout the entire width of the high-k dielectriclayer 105, and as such FIG. 5 shows the high-k layer 105 of the nFETgate stack 110 as having been completely oxidized by the lateraloxidation process.

Referring to FIG. 6, another embodiment of the present invention isillustrated where both the high-k dielectric layer 105 and thework-function conductor layer 106 are exposed to the lateral oxidationanneal process such that oxygen diffuses into both layers causing theoxygen content of the high-k dielectric layer 105 and the work-functionconductor layer 106 is increased first at the sidewalls of the gatestack 110 progress sing towards the center of the gate stack 110 as theduration of the oxidation anneal increases.

Referring to FIG. 7, the FET device 101 is shown as having had sidewallspacers 108 reapplied to the sidewalls of the gate stack 110 after atleast the high-k dielectric layer 105 has been oxidized to a desiredextent.

Referring to FIG. 8, another embodiment of the present invention isillustrated where the semiconductor structure 800 includes a nFET device802 and a pFET device 803. The semiconductor structure 800 contains ashallow trench isolation (STI) region 801 between the nFET 802 and thepFET 803. Each FET device contains a gate stack, 810 and 820. Each gatestack contains: a gate-insulator layer, 808 and 809; a high-k dielectriclayer, 811 and 812; a work-function conductor layer, 813 and 814; agate-conducting layer, 815 and 816; raised sources/drains, 806 and 807;and sidewall spacers, 817 and 818. The FET devices, 802 and 803, areboth disposed on a semiconductor layer 805, which resides on aninsulator layer 804.

In a preferred embodiment of the present invention, the gate stacks 810and 820 utilize the same material for the high-k dielectric layers, 811and 812, and also utilize the same material for the work-functionconductor layers, 813 and 814. Preferably the high-k dielectric layers,811 and 812, includes HfO2 and the work-function conductor layers, 813and 814, includes TiN. Using these materials causes the nFET 802 to havea low initial V_(T) and the pFET to have a high initial V_(T), which arethereafter respectively raised and lowered to V_(T) values desirable incertain preferred embodiments by applying an oxidation anneal process.This present invention is thereby able to reduce the complexity of CMOSprocessing, decrease the cost of fabrication, and increase the V_(T)stability of CMOS devices by utilizing the unconventional process ofsubjecting an nFET gate stack to a lateral oxidation anneal.

Referring to FIG. 9, an embodiment of the present invention isillustrated where the FET devices, 802 and 803, of the semiconductorstructure 800 have had any sidewall spacers, such as 817 and 818,removed from the FET devices, thereby exposing the sidewalls of therespective gate stacks, 820 and 810. Processes for selectively removingmaterial are well known in the art, such as those utilizing masks andetches involving diluted HF, and many may be used to remove material,such as the sidewall spacers 818 and 817, from the semiconductorstructure 800.

Referring to FIG. 10, application of the preferred lateral oxidationanneal process to the gate stacks, 810 and 820, of the nFET device 802and the pFET device 803, is illustrated, such that oxygen is shown asdiffusing into at least the high-k dielectric layers, 812 and 813. InFIG. 10, the high-k dielectric layers 812 and 811 of the respective gatestacks 810 and 820 are shown with arrows indicating the lateraloxidation anneal process increases the oxygen content of the high-klayers, 812 and 813, first at the sidewalls of the gate stacks 810 and820 due to how the high-k dielectric layers 812 and 811 are exposed tothe lateral oxidation anneal process. And as such the lateral oxidationanneal process diffuses oxygen from the sidewalls of the gate stacks 810and 820 towards the center of the gate stacks 810 and 820 as theduration of the process increases.

Referring to FIG. 11, both the nFET device 802 and the pFET device 803are shown as having been exposed to the oxidation anneal process for aduration sufficient to diffuse oxygen across the entire width of therespective high-k dielectric layers, 812 and 811, and as such FIG. 11shows the high-k dielectric layers, 812 and 811, as having beencompletely oxidized by the lateral oxidation anneal process such thatthe oxygen content has increased throughout the entirety of the high-kdielectric layers 812 and 811.

Referring to FIG. 12, the nFET device 802 and pFET device 803 are shownas having had material applied to the sidewalls of the respective gatestacks 810 and 820 to create sidewall spacers 818 and 817 after at leastthe high-k dielectric layers 812 and 811 have been subjected to anoxidation process. In FIG. 12, an embodiment of the present invention isillustrated with the high-k dielectric layers 812 and 811 having beenexposed to a lateral oxidation anneal process for a duration sufficientto diffuse oxygen across the entire width of nFET device 802 and pFETdevice 803.

Referring to FIG. 13, a further embodiment of the present invention isillustrated where the extent of oxidation occurring within the high-kdielectric layers 812 and 811 is not equal, such that the high-kdielectric layer 812 of the nFET device 802 is completely oxidized,while the high-k dielectric layer 811 of the nFET device 803 ispartially oxidized.

Referring to FIG. 14, another embodiment of the present invention isillustrated where the extent of oxidation occurring within the high-kdielectric layers of 812 and 811 is not equal, such that the high-kdielectric layer 812 of the nFET device 802 is partially oxidized whilethe high-k dielectric layer 811 of the pFET device 803 is completelyoxidized.

Referring to FIG. 15, another embodiment of the present invention isillustrated where the extent of oxidation having occurred within thehigh-k dielectric layers 812 and 811 is such that the high-k dielectriclayers 812 and 811 of both the nFET device 802 and the pFET device 803are partially oxidized.

Referring to FIG. 16, another embodiment of the present invention isillustrated. The embodiment lays out a method for forming asemiconductor circuit including obtaining a semiconductor structurehaving at least one gate stack of material layers that includes a layerof high-k dielectric material, laterally oxidizing at least the high-kdielectric material layer, and completely fabricating at least onen-type FET from the gate stack that includes a layer of laterallyoxidized high-k dielectric material; and also having the optional stepsof: performing an activation anneal on at least on gate stack, removingspacers from the sidewalls of at least one gate stack, and addingspacers to the sidewalls of at least one gate stack.

It will be apparent to those skilled in the art having regard to thisdisclosure that other modifications of the present invention beyondthose embodiments specifically described here can be made withoutdeparting from the spirit of the invention. For example, thesemiconductor devices and layered structures described above can includeadditional optional layers and the methods for fabricating such devicesand structures can include additional optional steps for depositing suchlayers. Accordingly, such modifications are considered within the scopeof the present invention as limited solely by the appended claims.

What is claimed is:
 1. A semiconductor structure, comprising: a n-typefield effect transistor having a high-k dielectric layer that has higherconcentration of oxygen at the sidewalls of the high-k dielectric layerthan at the center of the high-k dielectric layer.
 2. The semiconductorstructure of claim 1, wherein the high-k dielectric layer forms aportion of a gate stack.
 3. The semiconductor structure of claim 2,wherein the gate stack further comprises a work function conductorlayer.
 4. The semiconductor structure of claim 1, wherein the oxygen inthe high-k dielectric layer diffuses to a center of the high-kdielectric layer.
 5. The semiconductor structure of claim 1, wherein thehigh-k dielectric layer is completely laterally oxidized.
 6. Thesemiconductor structure of claim 1, wherein the oxygen in the high-kdielectric layer does not diffuse to a center of the high-k dielectriclayer.
 7. The semiconductor structure of claim 1, wherein the high-kdielectric layer is partially laterally oxidized.
 8. The semiconductorstructure of claim 1, further comprising a work-function conductor layeron the high-k dielectric layer.
 9. The semiconductor structure of claim8, wherein the work-function conductor layer comprises oxygen.
 10. Thesemiconductor structure of claim 9, wherein the oxygen of thework-function conductor layer increases near sidewalls.
 11. Asemiconductor structure, comprising: a n-type field effect transistorhaving a high-k dielectric layer that has higher concentration of oxygenat the sidewalls of the high-k dielectric layer than at the center ofthe high-k dielectric layer; and a p-type field effect transistor. 12.The semiconductor structure of claim 11, wherein the high-k dielectriclayer forms a portion of a gate stack.
 13. The semiconductor structureof claim 12, wherein the gate stack further comprises a work functionconductor layer.
 14. The semiconductor structure of claim 11, whereinthe oxygen in the high-k dielectric layer diffuses to a center of thehigh-k dielectric layer.
 15. The semiconductor structure of claim 11,wherein the high-k dielectric layer is completely laterally oxidized.16. The semiconductor structure of claim 11, wherein the oxygen in thehigh-k dielectric layer does not diffuse to a center of the high-kdielectric layer.
 17. The semiconductor structure of claim 11, whereinthe high-k dielectric layer is partially laterally oxidized.
 18. Thesemiconductor structure of claim 11, further comprising a work-functionconductor layer on the high-k dielectric layer.
 19. The semiconductorstructure of claim 18, wherein the work-function conductor layercomprises oxygen.
 20. The semiconductor structure of claim 19, whereinthe oxygen of the work-function conductor layer increases nearsidewalls.